Torrellas & Adve Named ACM Fellows

4/1/2011 5:46:00 AM ITI Staff

ITI professors Josep Torrellas and Sarita Adve have been named ACM Fellows for the class of 2010. Adve and Torrellas were recognized for their contributions to computing and computer science that have contributed fundamental knowledge to the field and generated a broad range of innovations in industry, commerce, entertainment, and education.

Written by ITI Staff

Josep Torrellas and Sarita Adve
Josep Torrellas and Sarita Adve
Josep Torrellas and Sarita Adve

ITI professors Josep Torrellas and Sarita Adve have been named ACM Fellows for the class of 2010. Adve and Torrellas were recognized for their contributions to computing and computer science that have contributed fundamental knowledge to the field and generated a broad range of innovations in industry, commerce, entertainment, and education.

The ACM Fellows Program, initiated in 1993, celebrates the exceptional contributions of the leading members in the computing field. These individuals have helped to enlighten researchers, developers, practitioners and end-users of information technology throughout the world. These new ACM Fellows join a distinguished list of colleagues to whom ACM and its members look for guidance and leadership in computing and information technology.

The Department of Computer Science is the home academic department for both Adve and Torrellas.

Sarita Adve

Adve was honored for her "impact on hardware and language memory models, and contributions to low-power and resilient systems." Adve's research in computer architecture and systems, parallel computing, and power and reliability-aware systems focuses on a full-systems view and is notable for its multidisciplinary collaborations.

Adve's broadest impact has been in hardware and software memory consistency models. She received the 2008 SIGARCH Maurice Wilkes award for this work, specifically "for formalization of memory consistency models, especially data-race free models, and their influence on both hardware and high-level languages."

The memory consistency model lies at the heart of the semantics of any threaded software or hardware. Arguably, it has been one of the most challenging and contentious areas in concurrent hardware and software specification for many years. There is finally now a convergence in both the hardware and software communities. Adve has been a common thread and a leader in the multiple community-scale efforts that have driven this convergence.

The memory consistency model is a hardware/software interface, affecting programmability and performance. Unfortunately, designing a model satisfying all desirable properties has proven difficult. Sequential consistency is simplest to program, but most systems do not provide it for performance reasons. Instead, we had divergent models (often ambiguously specified) for different hardware.

Her early work departed from the prevalent hardware-centric approaches to use a combined hardware/software view more appropriate for an interface. She observed that for well-synchronized programs (which she formalized as data-race-free), both sequential consistency and high performance can be provided. She developed a comprehensive framework to specify memory models as providing "sequential consistency for data-race-free programs." Adve's data-race-free model forms the foundation of the memory models for Java and C++. Adve has been a leader in power- and reliability-aware architectures. Her group was among the first to recognize that significant power reductions required breaking traditional system boundaries in favor of a collaborative, cross-layer, system-wide power management framework. The GRACE project she led was the first to demonstrate a prototype system where the hardware, operating system, network, and applications all adapted collaboratively to minimize energy while still meeting real-time quality of service requirements.

More recently, she has worked on hardware resiliency. Her research group, along with industrial collaborators, was the first to propose microarchitectural low-cost techniques for lifetime reliability. Her recent SWAT (SoftWare Anomaly Treatment) project has developed a very low-cost comprehensive resiliency framework that detects, diagnoses, and recovers from a variety of fault types. The key insight is that the hardware reliability solution need handle only the device faults that become visible to software and cause anomalous software behavior. SWAT employs almost zero-cost, always-on monitors to detect such software anomalies and invokes a sophisticated software-driven diagnosis and recovery mechanism only in the infrequent case of fault detection. SWAT has created significant excitement in industry; for example, it was featured in a forum on Emerging Reliability Issues for the IC Industry, sponsored by SRC/NIST/SEMATECH. SWAT is often credited for making software-driven solutions widely accepted as a promising approach for hardware resiliency.

Adve serves on the board of directors for the Computing Research Association and received the 2008 SIGARCH Maurice Wilkes Award. She received an IBM Faculty Award in 2005, was named a UIUC University Scholar in 2004, and received an Alfred P. Sloan Research Fellowship in 1998, an IBM University Partnership award in 1997 and 1998, and an NSF CAREER award in 1995.

She served on the National Science Foundation's CISE directorate's advisory committee from 2003 to 2005 and on the expert group to revise the Java memory model from 2001 to 2005. She co-led the Intel/Microsoft-funded Universal Parallel Computing Research Center (UPCRC) at Illinois as its director of research in its founding year (2008-09). She currently serves on the board of directors for ACM SIGARCH.

Josep Torrellas

Torrellas was honored for his "contributions to shared-memory multiprocessor architectures and thread-level speculation." His research interests are computer architectures, technologies, and organizations for shared-memory multiprocessors.

Torrellas is highly influential in the field of computer architecture. Of his over 170 refereed publications, 8 have received Best Paper Awards from top conferences. He ranks 4th and 7th among those with the most publications ever in the two top computer architecture conferences. He has graduated 27 Ph.D.s, of which 8 are now Assistant or Associate Professors at leading universities, including Cornell, Washington, Georgia Tech, NCSU, UCSC, Rochester, and OSU. Of them, six have NSF CAREER Awards.

Torrellas has made many seminal contributions in computer architecture. He described how the cache hierarchy and coherence protocol can support Thread-Level Speculation (TLS). He made groundbreaking advances by applying TLS to explicitly parallel programs. This enabled novel capabilities, such as speculative synchronization, on-the-fly concurrency debugging, low-overhead program monitoring, and aggressive memory access reordering in hardware while providing an easy interface to the parallel programmer.

Torrellas also proposed several new scalable server organizations, coherence protocols, and data prefetching schemes. He introduced embedded-ring snoopy cache-coherence protocols, for low-cost fast coherence. He described hardware-based incremental, in-memory checkpointing, for very low checkpointing overhead and recovery time in fault-prone environments. He contributed the first architecture model for process variation and aging, and many techniques to mitigate process variation and aging in tera-scale chips.

As part of his revolutionary Bulk Multicore architecture for parallel programming productivity, Torrellas developed a new execution model based on continuous execution of atomic blocks. This machine introduced path-breaking concepts such as logless support for deterministic replay of parallel programs, data race detectors based on novel signature and hashing hardware primitives, and microarchitecture to operate on groups of addresses at one time, for novel, high-performance compiler optimization.

Torrellas has been involved in many influential projects in multiprocessor computer architecture. In addition to the Bulk Multicore architecture, he led the Aggressive Cache Only Memory Architecture design, which was one of the Ten Point-Design Studies funded by the federal government in the nineties to accelerate the arrival of a petascale machine. He led the DARPA-funded Morphable Multithreaded Memory Tiles (M3T) architecture, and co-directed the NSF-funded FlexRAM Intelligent Memory system. He was one of the PIs for the DARPA-funded IBM PERCS multiprocessor project, which, under the HPCS program, led to the IBM Blue Waters supercomputer at NCSA. Before that, he worked in the teams that developed the Stanford DASH and Illinois Cedar experimental multiprocessors.

Torrellas is a chief architect and co-PI of the DARPA-funded Intel Runnemede multiprocessor. This is an extreme-scale multiprocessor being developed under the Ubiquitous High-Performance Computing program, and aims to reduce energy consumption per operation by between 100x and 1000x.

Torrellas has served the architecture community extensively. For five years, he has served as chair of the IEEE Technical Committee on Computer Architecture, where he contributed in a myriad of professional advancement activities. Before that, he served as vice-chair for four years, and he continues to serve on its Advisory Board. Torrellas has served in and influenced many initiatives from DARPA, NSF, DOE, NSA, NASA, and CRA. For example, he co-organized two CRA/CCC-sponsored community-wide workshops on Advancing Computer Architecture Research, and an NSF-sponsored workshop on US-India Research Collaboration. He is on the steering committees of several conferences and has for many years co-organized two influential yearly workshops on Scalable Shared-Memory Multiprocessors and Computer Architecture Evaluation Using Commercial Workloads. His group released the widely used SESC simulator of multiprocessor architectures.

At Illinois, Torrellas is the director of the Center for Programmable Extreme-Scale Computing, a center funded by DARPA, DOE, and NSF that focuses on architectures for extreme energy and power efficiency. He is also the leader of the UIUC OpenSPARC Center of Excellence. He is part of the Intel-Microsoft Universal Parallel Computing Research Center.

Torrellas is an IEEE Fellow since 2004 and was a Willett Faculty Scholar from 2002 to 2009. He has received several awards, including two Xerox Awards for Outstanding Faculty Research, an NSF Young Investigator Award, a Gear Outstanding Junior Faculty Award, an IBM Partnership Award, Intel Research Council Awards, and an NSF Research Initiation Award.

Contacts: Sarita Adve, 217/333-8461; Josep Torrellas, 217/244-4148.

Writer: Jennifer La Montagne, Department of Computer Science, 217/333-4049.

Released April 1, 2011


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This story was published April 1, 2011.